Broadcom Dual 100GbE CAUI4-to-CAUI4 PHY/Octal 25G Retimer - BCM81381
The BCM81381 is a low-power, low-latency PHY integrating retimer and equalizer functions that support 100-Gigabit Ethernet (GbE), 40GbE, 25GbE and 10GbE applications.
In 100G mode, the BCM81381 supports two full-duplex 100G ports (CAUI4-to-CAUI4) for SR4, LR4, and copper CR4 CFP2/CFP4/QSFP2 line-card applications.
In 40G mode, the BCM81381 supports two full-duplex 40GbE ports (XLPPI-to-XLAUI) for SR4, LR4, and copper CR4 QSFP+ line-card applications.
In 25G/10G mode, the BCM81381 supports 8x25GbE/10GbE ports for SR, LR, and copper CR/KR applications.
On-chip clock synthesis is performed by a low-cost 156.25 MHz reference clock (for all IEEE Standard 10G/40G/100G rates) via high-frequency, low jitter phase-locked loops (PLLs). Individual clock recovery is performed on the device by synchronizing directly to the respective incoming data streams.
The BCM81381 was designed in 16nm CMOS technology to provide a low-power, low-latency solution with integrated AC coupling capacitors for direct interfacing to Broadcom’s switch products. The BCM81381 is available in a 19mm x 19mm, 324-pin BGA, RoHS-compliant package.
In 40G mode, the BCM81381 supports two full-duplex 40GbE ports (XLPPI-to-XLAUI) for SR4, LR4, and copper CR4 QSFP+ line-card applications.
In 25G/10G mode, the BCM81381 supports 8x25GbE/10GbE ports for SR, LR, and copper CR/KR applications.
On-chip clock synthesis is performed by a low-cost 156.25 MHz reference clock (for all IEEE Standard 10G/40G/100G rates) via high-frequency, low jitter phase-locked loops (PLLs). Individual clock recovery is performed on the device by synchronizing directly to the respective incoming data streams.
The BCM81381 was designed in 16nm CMOS technology to provide a low-power, low-latency solution with integrated AC coupling capacitors for direct interfacing to Broadcom’s switch products. The BCM81381 is available in a 19mm x 19mm, 324-pin BGA, RoHS-compliant package.
Features
- Dual 100GE PHY supports CR4/SR4/LR4
- Clause 92 100G-CR4 transmit training
- Clause 91 100G FEC, bypassable
- Clause 85 40G-CR4 transmit training
- 25GbE mode with eight independent 25GBase-CR/SR/KR (per IEEE 802.3by) or 25GBase-CR1/KR1 (per 25G consortium specification)
- 50GbE mode with 50GBase-KR2 to 50GBase-CR2/KR2 (per 25G consortium specification)
- Support an intermix of 10GbE and 25GbE operations per lane across all eight lanes
- Low-speed CFP2/CFP4/QSFP2/QSFP+ Data I/O
- Low Power 16nm CMOS design
- High performance receive equalization >35dB channel loss
- 19x19mm BGA package, 1mm ball pitch
Applications
- Blade servers
- Enterprise LAN switching
- Line cards
- Routers
- Servers
- Switches
- Top-of-Rack switches
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