Fully integrated MSA-compatible multi-rate SONET/SDH/10GE/FEC transceiver operating at the OC-192/STM-64 (9.953 Gb/s), 10GE (10.3125 Gb/s), 10GFC (10.315 Gb/s) or one of three FEC (Forward Error Correction) (10.664/10.709, 11.096 or 11.31 Gb/s) data rates with serializer, deserializer, integrated clock multiplication unit (CMU), 10G clock, bus skew, limiting amplifier, data recovery circuit (CDR) and enhanced feature set.

 

On-chip clock synthesis is performed by the high-frequency, low jitter phase-locked loop (PLL) on the BCM8152 transceiver chip, allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. Clock recovery is performed on the device by synchronizing its on-chip voltage-controlled oscillator (VCO) directly to the incoming data stream. An on-chip phase detector and charge pump plus external VCXO implements a cleanup PLL. The cleanup PLL can be used to clean up the CDR recovered clock for loop timing applications or to clean up a noisy system clock.