A fully integrated serialization/deserialization (9.953/10.3125/10.5188-Gb/s) interface device performing the extension functions for a 10-Gigabit Serial Ethernet Reconciliation Sublayer (RS) interface.

 

The XGXS, PCS and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, WIS, Clock Multiplication Unit (CMU), and Clock and Data Recovery (CDR). For WAN applications, a WIS-compliant framer with flexible clocking modes allows transmission of Ethernet traffic over a WAN. On-chip clock synthesis is performed by the high-frequency low-jitter phase-locked loops for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing directly to their respective incoming data streams. Elastic buffers are provided to allow the XAUI and PMD interfaces to operate in asynchronous configuration. Only an external 155.52/156.25/159.38 MHz oscillator is required for the reference clock input.